The invention relates generally to extreme ultraviolet (EUV) lithography and, more particularly, to a method for fabricating an EUV lithography mask.
As semiconductor devices become more highly integrated and the design rule decreases, pattern sizes required for semiconductor devices have become finer. On the other hand, the wavelength of light used in a photolithographic apparatus has become shorter and shorter, and a Numerical Aperture (NA) of the photolithographic apparatus has reached its limit. Accordingly, technologies have been developed to overcome a limit resolution for the pattern, for example, immersion lithography, Double Patterning Technology (DPT), and Extreme Ultraviolet (EUV) lithography.
The EUV lithography process uses EUV, the wavelength of which is shorter than KrF or ArF light, to form a pattern less than 32 nm. In a mask used in the EUV lithography, a reflecting layer in which MO/Si layers are repeatedly stacked is disposed on a substrate and an absorber pattern is disposed on the reflecting layer with a shape of the pattern to be transferred onto a wafer. When the EUV is irradiated on the EUV lithography mask, the EUV is absorbed at the absorber layer pattern and reflected at a surface of the reflecting layer.
The EUV irradiated in the EUV lithography process is irradiated or reflected with an angle of incidence inclined with respect to a mask surface, e.g. with an angle of incidence of 5° to 6°, rather than vertically. At this time, a height difference between the overlying absorber layer pattern and the underlying reflecting layer may cause a shadow portion at which the EUV is not irradiated or reflected. Therefore, the degree of shading by the absorber layer pattern is varied with the position on the wafer, resulting in a shadow effect in that a Critical Dimension (CD) of the wafer pattern is varied since a direction along which the EUV is incident to the mask is varied little by little as the position on the wafer to which the EUV is incident.